# frv testcase for umulcc $GRi,$GRj,$GRk
# mach: all

	.include "testutils.inc"

	start

	.global umulcc
umulcc:
	set_gr_immed   	3,gr7		; multiply small numbers
	set_gr_immed   	2,gr8
	set_icc         0x0f,0		; Set mask opposite of expected
	umulcc      	gr7,gr8,gr8,icc0
	test_icc	0 0 1 1 icc0
	test_gr_immed  	0,gr8
	test_gr_immed  	6,gr9

	set_gr_immed   	1,gr7		; multiply by 1
	set_gr_immed   	2,gr8
	set_icc         0x0e,0		; Set mask opposite of expected
	umulcc      	gr7,gr8,gr8,icc0
	test_icc	0 0 1 0 icc0
	test_gr_immed  	0,gr8
	test_gr_immed  	2,gr9

	set_gr_immed   	2,gr7		; multiply by 1
	set_gr_immed   	1,gr8
	set_icc         0x0f,0		; Set mask opposite of expected
	umulcc      	gr7,gr8,gr8,icc0
	test_icc	0 0 1 1 icc0
	test_gr_immed  	0,gr8
	test_gr_immed  	2,gr9

	set_gr_immed   	0,gr7		; multiply by 0
	set_gr_immed   	2,gr8
	set_icc         0x0b,0		; Set mask opposite of expected
	umulcc      	gr7,gr8,gr8,icc0
	test_icc	0 1 1 1 icc0
	test_gr_immed  	0,gr8
	test_gr_immed  	0,gr9

	set_gr_immed   	2,gr7		; multiply by 0
	set_gr_immed   	0,gr8
	set_icc         0x0a,0		; Set mask opposite of expected
	umulcc      	gr7,gr8,gr8,icc0
	test_icc	0 1 1 0 icc0
	test_gr_immed  	0,gr8
	test_gr_immed  	0,gr9

	set_gr_limmed 	0x3fff,0xffff,gr7	; 31 bit result
	set_gr_immed   	2,gr8
	set_icc         0x0f,0		; Set mask opposite of expected
	umulcc      	gr7,gr8,gr8,icc0
	test_icc	0 0 1 1 icc0
	test_gr_immed  	0,gr8
	test_gr_limmed 	0x7fff,0xfffe,gr9

	set_gr_limmed  	0x4000,0x0000,gr7	; 32 bit result
	set_gr_immed   	2,gr8
	set_icc         0x0e,0		; Set mask opposite of expected
	umulcc      	gr7,gr8,gr8,icc0
	test_icc	0 0 1 0 icc0
	test_gr_immed  	0,gr8
	test_gr_limmed 	0x8000,0x0000,gr9

	set_gr_limmed  	0x8000,0x0000,gr7	; 33 bit result
	set_gr_immed   	2,gr8
	set_icc         0x0d,0		; Set mask opposite of expected
	umulcc      	gr7,gr8,gr8,icc0
	test_icc	0 0 0 1 icc0
	test_gr_immed  	1,gr8
	test_gr_immed  	0x00000000,gr9

	set_gr_limmed  	0x7fff,0xffff,gr7	; max positive result
	set_gr_limmed  	0x7fff,0xffff,gr8
	set_icc         0x0d,0		; Set mask opposite of expected
	umulcc      	gr7,gr8,gr8,icc0
	test_icc	0 0 0 1 icc0
	test_gr_limmed 	0x3fff,0xffff,gr8
	test_gr_immed  	1,gr9

	set_gr_limmed  	0x8000,0x0000,gr7	; max positive result
	set_gr_limmed  	0x8000,0x0000,gr8
	set_icc         0x0d,0		; Set mask opposite of expected
	umulcc      	gr7,gr8,gr8,icc0
	test_icc	0 0 0 1 icc0
	test_gr_limmed 	0x4000,0x0000,gr8
	test_gr_immed  	0,gr9

	set_gr_limmed  	0xffff,0xffff,gr7	; max positive result
	set_gr_limmed  	0xffff,0xffff,gr8
	set_icc         0x05,0		; Set mask opposite of expected
	umulcc      	gr7,gr8,gr8,icc0
	test_icc	1 0 0 1 icc0
	test_gr_limmed 	0xffff,0xfffe,gr8
	test_gr_immed  	1,gr9

	pass
